Fast allocation of post-silicon tunable buffers to mitigate timing variation

It is widely accepted that post-silicon tunable (PST) buffer, which can adjust its delay after manufacturing, is an effective design element that can mitigate the timing variation in circuits. However, since the size of PST buffer is not that small, it is very important to minimize the number of PST buffers to be allocated while meeting the timing yield constraint. Recently, two noticeable progresses have been made in the literature: (1) one is devising a formulation of ‘timing criticality’ which facilitates identifying a set of circuit paths that are more likely to be susceptible to the timing variation; (2) the other is developing a graph based timing representation which enables a fast timing yield computation. In this work, we exploit the two features of (1) and (2) on the PST buffer allocation. Namely, we extract timing critical paths according to (1), rather than relying on a simple rule of thumb, and iteratively allocate PST buffers to resolve the timing criticality based on the fast timing yield computation according to (2), instead of using a very slow Monte-Carlo simulation. Through experiments with benchmark circuits, it is shown that our proposed PST buffer allocation methodology speeds up the PST allocation by 10x∼10000x over a Monte-Carlo simulation based approach. Furthermore, when compared with that produced by a full PST buffer allocation, ours is able to use 89.5% less number of PST buffers on average.