Analysis of soft errors in floating channel type surrounding gate transistor (FC-SGT) DRAM cells

This paper clarifies alpha-particle-induced soft error mechanisms in FC-SGT DRAM cells. FC-SGT DRAM cell arranges bit-line (BL), storage node and body region in a silicon pillar vertically and achieves cell area of 4F 2 per bit. In FC-SGT DRAM cells, the parasitic bipolar current is a significant factor to cause soft error. When an alpha particle penetrates the silicon pillar, generated electrons are collected to storage node or BL due to funneling and diffusion mechanisms. On the other hand, holes are swept into the body region and accumulated. Due to the floating body effect, the current flows not only in the surface but also in the entire body region, resulting in the loss of the stored charge. The surrounding gate structure, however, can suppress the parasitic bipolar current compared with planer SOI DRAM cell. Therefore, FC-SGT DRAM is a promising candidate for future high density DRAMs having high soft error immunity.