Gate-Leakage Current Mechanisms in Silicon Field-Effect Solar Cells

Field-effect solar cells (FESCs) are increasingly attractive for 2-D heterojunction solar cells and especially for gate-tunable Schottky-junction solar cells. A prerequisite for applying FESCs is that the gate-leakage (GL) power must be far less than the output power. However, the conduction mechanism of the GL current in a FESC has yet to be described clearly, thereby leading to excessive gate power consumption. In this work, the GL current mechanisms for a silicon FESC are extracted and analyzed using temperature-dependent current–voltage measurements under dark and illuminated conditions. It shows that the GL current for a FESC in the dark is dominated by both temperature-dependent Poole–Frenkel (P–F) emission and hopping conduction, whereas, under illumination changes to the temperature-independent space-charge-limited (SCL) current. Furthermore, whether the incident light power of 62.5, 100, or 125 mW/cm2 is used, or the gate dielectric of SiO2 is replaced by HfO2, the dominant GL current mechanism is consistent. Finally, the trap energy level is approximately calculated as 0.38–0.72 eV based on a P–F emission analysis; the mean trap spacing of 0.01–0.18 nm and the activation energy of approximately 0.02 and 0.05 eV are extracted by a hopping conduction analysis. Meanwhile, a rigorous SCL conduction analysis provides a carrier mobility of 1.4 × 10−8 cm2·V−1·s−1 in SiO2 and 5.3 × 10−8 cm2·V−1·s−1 in HfO2.