EUV single patterning for logic metal layers: achievement and challenge (Conference Presentation)

imec’s investigation on EUV single patterning insertion into industry 5nm-relevant logic metal layer is discussed. Achievement and challenge across imaging, OPC, mask data preparation and resulting wafer pattern fidelity are reported with a broad scope. Best focus shift by mask 3D of isolated feature gets worse by the insertion of SRAF, which puts a negative impact on obtaining large overlap process window across features. imec’s effort across OPC including SMO and mask sizing is discussed with mask rule that affects mask writing. Resist stochastic induced defect is identified as a biggest challenge during the overall optimization, and options to overcome the challenge is investigated. For mask data preparation, dramatic increase in the data volume in EUV mask manufacturing is observed from iArF multiple patterning to EUV single patterning conversion, particularly by the insertion of SRAF. In addition, logic design consideration to make EUV single patterning more affordable compared to alternative patterning option is be discussed.