Modeling of single/multiple-bit upset effects on logic circuits applying Recurrent Neural Network

Abstract This paper proposes a Recurrent Neural Network (RNN) method for modeling transient fault effects on microelectronic devices. RNNs can estimate the impacts of glitches propagated through the circuits, fast and accurately. The estimation phase begins with the learning of behavior of the gates, i.e., NOT, AND, NAND, etc. Then, it provides fast and meticulous evaluations of the transient fault influences on circuits. Simulation results illustrate that the RNN develops the capabilities of conventional methods to explicit forms and impacts of transient faults. The findings accrued from RNN analysis of a 32-bit multiplier, demonstrate 2736x time speed-up with the 4.13 of accuracy loss in contrast with the HSPICE’s simulation time and output values. Additionally, in terms of estimating multiple transient fault effects on the 4-bit Multiply and Accumulate (MAC) circuit, compare to HSPICE’s, there is 16.69x time-acceleration with the 0.048 penalties in output signals’ values. The model considers the triple masking effects, re-convergent fan-out, and fault influences during several clock cycles.