Mitigating charge spill-back induced image lag with a multi-level transfer gate pulse in PPD image sensors

A new method for minimizing image lag due to charge spill-back has been developed for pinned photodiode CMOS image sensors. The proposed method involves the use of multi-level transfer gate voltage during a single charge transfer period. Measurement results show that the new transfer process maintains the lower values for image lag at low signal levels that a high transfer gate voltage grants, whilst simultaneously preserving the later onset of spill-back dominated lag that a lower transfer gate voltage allows.