Voltage-controlled negative resistance in a submicron vertical JFET

Abstract A conspicuously sharp voltage-controlled negative resistance (NR) has been observed in a scaled-down, sub-micron vertical JFET. This JFET has a “surface-electrode” structure in which both source and gate layers lie only on the surface of the silicon substrate. Source layer size is 0.6 × 0.6 μm, and gate-source spacing is 0.2 μm. The present JFET has been fabricated with a self-aligning process employing a novel amorphous material, SiGeB ternary alloy. In order to obtain a condition in which NR occurs, two-dimensional computer simulation has been carried out. This simulation has shown that conditions necessary for NR are also appropriate for high-speed operation of a scaled-down bipolar-mode JFET. A logic gate configuration taking advantage of this negative resistance has been devised.