Edge effect aware low-power crosstalk avoidance technique for 3D integration

Abstract Metal wires and through silicon vias (TSVs) are frequently performance bottlenecks of 3D ICs due to their high capacitive crosstalk which can be reduced using coding techniques. In this work we show that existing TSV crosstalk avoidance codes (CACs) are impractical for real applications due to the edge effects in TSV bundles. Additionally, these 3D CACs do not reduce the metal wire crosstalk and dramatically increase the power consumption of 2D and 3D interconnects. This work presents a 3D CAC which overcomes previous limitations. The method is based on an intelligent fixed mapping of the bits of existing 2D CACs onto rectangular or hexagonal TSV arrangements. Simulation results, obtained by circuit simulations in combination with an electromagnetic field solver, show that existing 3D CACs only reduce the TSV crosstalk by a maximum of 9.4%, provide no optimization of the metal wire crosstalk and induce an increase in the interconnect power consumption by about 50%. In contrast, the presented technique requires less hardware and reduces the maximum crosstalk of modern TSV and metal wire buses by 37.8% and 47.6%, respectively, while leaving their power consumption almost unaffected. Alternatively, our technique can reduce the TSV and metal wire crosstalk peaks by 20.3% and 47.7%, respectively, while additionally providing a reduction in the TSV and metal wire power consumption by 5.3% and 21.9%, respectively.