Scaling scenario of floating body cell (FBC) suppressing V th variation due to random dopant fluctuation

A scaling scenario of fully-depleted floating body cell (FBC) is demonstrated in view of signal margin for stable array functionality. Measurement and numerical simulation reveal that the Vth variation of cell array transistors is mainly attributed to the random dopant fluctuation in channel region. By setting the channel impurity concentration in the order of 10 16 cm -3 or lower, Gbit array functionality is guaranteed for the 32nm node and further scaled generations.