Bridging Lithography Processes with NAND Flash ECC Complexity

The NAND Flash memory is the technological driver for both critical dimensions scaling and process technologies. In order to keep pace with the Moore's Law, the scale chip dimensions decrease to the point where variability effects become significant. Particularly, when printed features go down below the 20 nm, transistors structures are strongly affected by pattern roughness caused by the randomness in advanced lithographies (e.g. Extreme UV), leading to variability induced data errors in the memory functionality. Two treatments for variability are known: roughness smoothing processes at the process stage and on-chip error correcting algorithms. This paper describes a holistic framework, which trades-off between lithography processes and error control codes complexity to ensure data integrity in probabilistic 16 nm memories.