Investigation of negative DIBL effect for ferroelectric-based FETs to improve MOSFETs and CMOS circuits

Abstract In this study, negative DIBL (NDIBL) due to negative capacitance is used to improve MOSFETs and Complementary Metal-Oxide-Semiconductor Transistor (CMOS) circuits by employing custom-built Simulation Program with Integrated Circuit Emphasis (SPICE) model. A multi-threshold technique was proposed by using NDIBL effect, and it can be manufactured by simple manufacturing process without increasing footprint of transistor. The influence of the negative DIBL effect of a negative capacitance field-effect-transistor (NCFET) on transistor effective drive current (Ieff) and CMOS circuit performance were analyzed. The results shown that increasing NDIBL effect increased Ieff by ~12%. A 7-stage ring oscillator (RO) was simulated to analyze the CMOS circuit energy-delay, and it shown that significant delay reduction, at iso-energy and iso-area, can be achieved owing to NDIBL effect of NCFET. A 6T Static Random-Access Memory (SRAM) cell was investigated, and enhanced hold and read static noise margins (SNM) are achieved owing to NDIBL effect. Moreover, several methods of increasing NDIBL effect were proposed.