A 0.4-V high-speed, long-retention-time DRAM array with 12-F/sup 2/ twin cell

We propose and evaluate a DRAM cell array with 12-F/sup 2/ twin cell in terms of speed, retention time, and low-voltage operation. The write time and retention time of the twin-cell array become shorter by 50% and longer by more than 20% than those of a single cell array, enabling a 0.4-V operation. Furthermore, the cell accepts the plate-driven scheme without dummy cell, lowering the necessary word-line voltage by 0.4 V.