Wafer-level RF test and DfT for VCO modulating transceiver architectures

Traditionally, radio frequency (RF) paths are bypassed during wafer sort due to the high cost of RF testing. Increasing packaging costs, however; result in a need for a more thorough wafer-level testing including the RF path. In this paper, we propose a loop-back architecture, along with a novel, all-digital design-for-testability (DfT) modification that enables cost efficient testing of various defects at the wafer level. These methods are applicable to a wide range of cost-sensitive applications that use the modulation of the voltage-controlled-oscillator (VCO). Experimental results using a Bluetooth platform and considering a variety of defects confirm the viability of the approach.