Design of high-linearity delay detection circuit for 10-Gb/s communication system in 65-nm CMOS

We have proposed a transmission system of the additional data by using frequency modulation technique. In a receiver, demodulation characteristics deteriorate according to data speed. In the previous work, we showed the emphasis technique can reduce the degradation in demodulated signal. In this paper, we designed the delay detection circuit on the basis of the detailed analysis. To investigate the proposed circuit, we fabricated the delay detection circuit with emphasis using 65-nm CMOS process. We confirmed the improved linearity in demodulated signal, which indicate our proposed circuit can be applicable to the 10-Gb/s demodulating systems.