Design of All Digital SARDLL for DVFS System-on-Chip

An all digital fast-locking Successive Approximation Register-controlled Delay-Locked Loop( SARDLL) with w ide-range operating frequency and constant acquisition cycles is presented for the clock synchronization of Dynamic Voltage / Frequency Scaling( DVFS) System-on-Chip( So C). The improved resettable Digitally Controlled Delay Line( DCDL) scheme is adopted to effectively solve the harmonic lock problem and zero-delay problem of the conventional all digital SARDLL,meanw hile reduces the hardw are overhead and increases the maximum operating frequency. The presented all digital SARDLL is implemented using the TSM C-65 nm CM OS standard cell library. Based on the typical corner and25℃,the post-layout simulation results show that the operating frequency range is from 250 M Hz to 2 GHz,the lock time is18 cycles of the input clock signal and the pow er consumption is 0. 4 m W at 2 GHz and 1. 2 V supply voltage.