A Modified Signal Flow Graph and Corresponding Conflict-Free Strategy for Memory-Based FFT Processor Design

This brief presents a modified radix-4 fast Fourier transform (FFT) signal flow graph, whose input and output both are in natural order. Compared with the conventional radix-4 signal flow graph, it does not buffer the result of the last stage or execute the bit-reverse operation to generate the result, but generates the result directly in the last stage. Thus, the number of iterations is reduced by one. In order to realize the proposed memory-based FFT processor by using the modified radix-4 FFT signal flow graph, a conflict-free strategy and corresponding memory-addressing scheme is proposed. At last, the hardware implementation for the proposed FFT processor is proposed. Through the adoption of this method, FFT processor of arbitrary point conforming to the radix-4 algorithm can be implemented. Compared with the previous memory-based FFT processors, the proposed FFT processor has less processing time under similar or lower resource consumption.