A Hardware-Efficient Parallel Architecture for HEVC Deblocking Filter

The deblocking filter (DBF) constitutes an important part of the High Efficiency Video Coding (HEVC) standard. In this paper, a novel hardware architecture of the HEVC DBF is proposed for all block boundaries within a luma $32 \times 32$ coding block (CB) to reduce visual artifacts. The proposed hardware architecture employs a high degree of parallelism and includes pipeline structure in order to improve the throughput. Experimental results demonstrate that the proposed DBF architecture can reach a high operating clock frequency of 250 MHz and can support $3840\times 2160@50fps$ real-time applications on the Zynq system-on-chip (SoC).