Investigation of strained Si/SiGe devices by MC simulation

Abstract Transport in Si NMOSFETs with gate lengths from 48 to 23 nm is investigated by full-band Monte Carlo device simulation for three sets of devices: (I) unstrained Si control devices , (II) process matched strained Si devices, and (III) threshold voltage matched strained Si devices. While the process matched strained Si devices show the same performance improvement for all gate lengths, this is not the case for the threshold voltage matched devices for which the performance improvement degrades with shrinking gate length due to the heavier doping.