Implementation of a Decimal Divider using a Hybrid Method

This paper proposed an implementation of a hybrid decimal division algorithm to enhance division speed and it’s implementation. The proposed hybrid algorithm employed either non-restoring or restoring technique (algorithm) on each digit to reduce iterative computations based on the relative remainder values with respect to the half of its divisor. The hybrid decimal divider design addressed rapid operations. Dividers were synthesized using a 0.18 ㎛ CMOS standard cell library for performance comparison purposes. For a 16 digit quotient, the number of computations for the proposed hybrid divider is reduced 36.5 % and 29 % less than the conventional restoring and the non-restoring dividers, respectively.