A 16-mW, 120-dB linear switched-capacitor delta-sigma modulator with dynamic biasing

A high-resolution, fourth-order /spl Delta//spl Sigma/ analog-to-digital converter is presented. Power-reduction techniques have been applied across many aspects of the design. A class-A amplifier was designed with bias currents optimized according to the expected activity in each clock phase. The modulator achieves a 122 dB dynamic range over a 400-Hz bandwidth, -123-dB total harmonic distortion, and 16-mW power consumption from a single 5-V supply. It is implemented in a 0.6-/spl mu/m double-polysilicon CMOS process and has an active area of 2 mm/sup 2/.