Low latency turbo decoder implementation for future broadcasting systems

As a class of high-performance forward error correction codes, turbo codes, which can approach the channel capacity, could become a candidate of the coding methods in future broadcasting systems. High throughput and low latency are two basic requirements that the future systems need to meet. Parallel turbo decoding is a very effective method to reduce the latency and improve the throughput in the decoding stage. In this paper, a parallel turbo decoder is designed and implemented in field-programmable gate array (FPGA). A reverse address generator is proposed to reduce the complexity of interleaver and also the iteration time. The latency of parallel turbo decoder after implementation can be as less as 23.2us at a clock rate of 250 MHz and the throughput can reach up to 6.92Gbps.