Co-optimization of PDN Design for Tri-cluster Multiple CPU Cores of SOC with various decoupling capacitors integrated in Small Form-Factor Package

In this paper, PI (Power Integrity) performance of interposer package-on-package (POP) is analyzed with respect to types of package decoupling capacitors and relative location of package decoupling capacitors to CPU (Central Processing Unit) PDN (Power Distribution Network) of package. Packages with the decoupling capacitor within SOC package substrate, and that on bottom ball land side are being analyzed and compared in terms of system-level core PDN impedance. Moreover, decoupling capacitor’s placement with respect to that of CPU cores are being analyzed. In addition to the PI performance improvement of the package using decoupling capacitor, the system-level PI performance were analyzed and improved through co-optimization of on-chip PDN.