A foreground digital calibration by switching control scheme for A 12-bit SAR ADC

This paper proposed a digital method to calibrate nonlinearity caused by capacitor mismatch and parasitic capacitors in the split-capacitor DAC for a 12-bit 50 MS/s SAR ADC. By applying foreground switching control scheme and without additional analog circuits, a group of calibration indexes are measured and added to the output codes to compensate the conversion error. Simulation results obtained from a 65nm CMOS LP process prototype ADC shows that SFDR at 20.6 MHz input and 1.2 V supply can be improved from 66.52 dB to 76.13 dB. DNL/INL are measured as +0.68∼−1 LSB/+3.59∼−3.61 LSB and corrected to +1.62∼−0.1 LSB /+1.73∼−1.61 LSB respectively.