The design of a 0.33 THz frequency tripler

In this paper, we use suspended microstrip to design a 0.33 THz fequency tripler, in which a pair of Schottky varactor chips parallel is adopted. Considering the present processing technology, it's easy for the unbalanced structure to provide bias to the diodes without an on-chip capacitor, which is essential to the balanced tripler scheme. The tripler consists of a waveguide housing, a pair of quartz microstrip circuits, a Rogers RT/duroid 5880 (tm) DC bias filter and a GaAs Schottky varactor chip. And when the input power is 23 dBm, The whole circuits simulation results indicates that the output power with 12.96% efficiency at 330.9 GHz, The 3 dB bandwidth for the tripler is above 7%.