A New Approach for Estimation of On-Resistance and Current Distribution in Power Array Layouts

This paper presents an accurate and fast technique for the estimation of on-resistance (R DS(on) ) of large lateral power MOSFET switch layouts in on-chip DC-DC converter and determination of the current distribution pattern in the switch layouts. In the proposed approach an extracted netlist is created which consists of the lumped parasitic resistances formed in the metal interconnects and the MOS devices present in the layout. The extracted resistance values are computed from the metal geometry using models that relate resistance values to the geometric patterns in the layout. This approach exploits the highly symmetric and repetitive pattern of power MOSFET layouts to generate the resistance netlist efficiently. Similarly the modeling of very high W/L MOS finger channels is also described in this paper. Results from the numerical experiments show that the extracted resistances are within 2.6% of results obtained from standard FEM solver tool ANSYS.