A quick-turn 3D structured ASIC platform for cost-sensitive applications

This paper presents a novel 3D structured ASIC platform that lowers the development effort required to deploy 3D integration technologies in cost sensitive, low-volume applications. The key advantage of this structured 3D ASIC architecture, over custom 3D ASICs, is a fixed vertical interconnect pattern that is programmed by a single 2D metal-via mask, allowing individual die levels to be rapidly designed, fabricated, and assembled. The first silicon realization of this architecture is a 3D-stackable 12×12mm structured ASIC die with 42K interconnects, which is resource compatible with an existing 2D structured ASIC device of the same size. 3D die stacks built using this platform are also intended to be a less costly and more flexible replacement for a large 20×20mm monolithically integrated structured ASIC device. This 3D structured ASIC platform was des igned and fabricated in Sandia's 0.35-μm foundry, and high-density front-end-of-line through silicon vias (TSVs) were developed to implement the 3D vertical interconnects 1 .