Flatband Voltage Tuning of HfSiON-based Gate Stacks: Impact of High Temperature Activation Annealing and LaOx Capping Layers

INTRODUCTION The aggressive scaling of metal-oxide-semiconductor field-effects transistors (MOSFETS) faces the challenge of metal gate (MG) and high-k (HK) dielectric integration to reduce power consumption [1]. Hf-based oxides and silicates, such as HfSiON, are considered as the most promising candidates for next-generation gate dielectrics, owing to their high permittivity, with a sufficiently wide band gap and a good thermal stability [2]. However, the control of the threshold voltage (Vth) for the advanced nFET and pFET devices is challenging [3]. In gate first approach, the incorporation of LaOx capping layer has been reported to provide Vth shift towards the nFET band edge, yielding the necessary decrease of the effective work function (EWF) of the gate [4]. The mechanism of this voltage shift is attributed to La-induced dipoles at the HK/Si interface [5]. For this reason, the location of LaOx capping layer within the gate stack is a key factor for optimizing the transistor Vth. So far, detailed studies of La-capped gate systems have been focused on HfO2/SiO2 stacks. In this work, we have investigated the impact of high temperature thermal annealing and LaOx capping layer on electronic structure and band discontinuity for TiN/LaOx/HfSiON/SiON/Si gate stacks by coupling hard X-ray photoelectron spectroscopy (HAXPES) with synchrotron radiation and capacitance versus voltage (CV) measurements.