Evidence for ferroelectric border traps near the SrBi2Ta2O9/Si interface through capacitance–voltage measurement

A metal–ferroelectric–semiconductor (MFS) structure has been developed by depositing SrBi2Ta2O9 (SBT) films directly on n-type (100) Si by pulsed laser deposition. In the MFS structure, evidence for ferroelectric border traps in the SBT film has been obtained by high-frequency capacitance–voltage (C–V) measurement. When the ramp rate of voltage is higher than 200 mV/s, typical ferroelectric C–V hysteresis loops with the counterclockwise direction are obtained in C–V plots. When the ramp rate is lower than 80 mV/s, the ferroelectric hysteresis loops are replaced by the trap-induced ones with the clockwise direction. This pronounced change results from the fact that more and more border traps in SBT can communicate with the underlying Si. The border-trap density at the ramp rate of 10 mV/s is as high as 1.8×1012 cm−2. Moreover, the width of the hysteresis loops changes linearly with the logarithmic decrease in ramp rate, which is consistent with the ferroelectric border traps communicating with Si by tunnel...