LOW-POWER 1-BIT FULL-ADDER CELL USING ENHANCED PASS TRANSISTOR LOGIC AND POWER GATING

Adders have become one of the important components in the digital world, such that there exists no design without it. Adders are not only used for additions, but it is also one of the basic building blocks that have been used for many other functions such as subtractions, multiplications, and divisions etc. In the field of Very Large Scale Integration (VLSI), Adders are used as the basic component from processors to ASICs. Propagation delay, Power and Area are the acceptable Quality metrics of the designed products. Recent days has proved that the use of Complementary Pass Transistor Logic (CPL) and sleep transistor provides a drastic reduction in the power compared to CMOS logic. Power Gating is one such well known technique where a sleep transistor is added between actual ground rail and circuit ground. The device is turned off during sleep mode to cut-off the leakage path. This technique results in a substantial reduction in leakage at a minimal impact on performance. This paper has spread the focus on Low power Adder design based on PTLs, with reduced sub threshold leakage power consumption and ground bounce noise during sleep to active mode transition, thereby achieving 2.5% reduction in power without affecting other quality metrics of the design. The CPL design has been modeled and analyzed using TANNER EDA with TSMC MOSIS 250nm technology. In the present paper we will propose low leakage 1 bit CMOS full adder circuit in 90nm technology with supply voltage of 1V.