Reliability analysis of bumping schemes under chip package interaction

Reliability analysis for three bumping configurations is performed under typical chip package interaction. A sequential submodeling technique is employed to capture stress evolution during entire package assembly process. Mechanical stresses are assessed in various regions around bumps to determine the optimal bumping scheme with the minimal reliability risk. Underfill material property impact on package reliability is also examined. This study provides important guidelines to design robust bumping configurations with fine-tuned material properties.