Hierarchical Verification of AMS Systems with Affine Arithmetic Decision Diagrams

Formal methods are a promising alternative to simulation-based verification of mixed-signal systems. However, in practice, such methods fail to scale with heterogeneity and complexity of today’s analog/mixed-signal systems. Furthermore, it is unclear how they can be integrated into existing verification flows. This article shows a path to overcome these obstacles. The idea is to use a hierarchical verification flow, in which components can be verified by formal methods or by multi-run simulation. To transport verification results across hierarchies, we represent parameters and properties by affine arithmetic decision diagrams. We study to which extent this approach fulfills the needs of practical application by the verification of a phase-locked loop (PLL) of an IEEE 802.15.4 transceiver system.