Power-Efficient Approximate Multiplier Using Adaptive Error Compensation

In this paper, a design framework is proposed for a power-efficient approximate multiplier using adaptive error compensation and the optimal error compensation values are determined by using probability theory, resulting in a minimal mean-squared-error (MSE). To further pursue the viability of adaptive accuracy, adaptive error compensation scheme using different levels of quantization is utilized for the predetermined compensation values. The simulation results show that the approximate multipliers based on the proposed design framework outperform state-of-the-art designs in both accuracy and circuit measurements. Specifically, with a higher accuracy, the proposed designs save up to 36.84% and 21.61% in power consumption compared to state-of-the-art unsigned and signed approximate $16\times16$ multipliers, respectively. In terms of power-delay-product (PDP), the improvements are up to 42.3% and 21.93% for the unsigned and signed multiplier designs, respectively. Finally, the approximate multipliers are further assessed in the implementation of an FIR filter. It shows that the proposed approximate multiplier achieves a similar filtering quality to the accurate design, with more than 50% reduction in power dissipation.