Performance and Analysis of Stack Junctionless Tunnel Field Effect Transistor

To overcome the fabrication complexity and achieve a better switching ratio is a major grave concern for applications in semiconductor devices. In this regards, a novel stack gate-oxide junctionless double-gate tunnel field effect transistor with low work-function livestrip (LWLS-SGO-JL-TFET) has been investigated in this manuscript. This structure serves as an alternative solution to improve the performance of device. For this, device structure has comprised of two isolated gates such as polarity gate and control gate with the platinum (work-function = 5.93 eV) and hafnium (work-function = 4.3 eV) respectively, over the N+-type doped silicon substrate for the formation of Tunnel Field Effect Transistor as a like doped conventional TFETs (Tunnel Field Effect Transistors) to overcome fabrication complexity. Since ON state current plays important role in switching ratio and subthreshold swing. Therefore, a dual layer oxide (stack) has introduced in junctionless TFETs to get further improvement in ON state current due to the better capacitive coupling between gate and substrate. Under this condition, the performance improvement is still required of dual oxide juntionless TFETs. Hence, a live strip has inserted at the source side in dual oxide layer to improve the ON state current which helps in gain of device and design of analogue and RF circuits. Moreover, we have also examined the impact of low work-function of live strip on dual oxide Junctionless TFETs in terms of DC, analog/RF and linearity figures of merit (FOMs) of the device. All simulation have been carried out using the technology computer aided design (TCAD) tool. This study shows that proposed device is an appropriate for ultra low power high frequency applications.