Strain Stability and Carrier Mobility Enhancement in Strained Si on Relaxed SiGe-on-Insulator

A low thermal budget process to fabricate strained Si metal-oxide-semiconductor field-effect transistors (MOSFETs) on a strain-relaxed silicon-germanium-on-insulator (SGOI) by strain engineering is described. The strain stability in the top strained Si is studied after low temperature oxidation, ion implantation, and rapid thermal annealing, and only 7-9% relaxation is observed. The Ge content distribution in a strained-silicon-on-insulator (SOI) is investigated to validate the process with a low thermal budget. Ge, reaching the strained Si/SiO 2 interface, inevitably degrades the gate oxide properties. The electron and hole mobility values in the biaxial strained-SOI are investigated and compared to those in MOSFETs fabricated in strain-relaxed SGOI and SOI substrates. Both carrier mobilities are enhanced, and the process is much simpler than using uniaxial strained Si. The relaxed-SGOI MOSFETs possess the lowest carrier mobility, and both the electron and hole mobility values in the strained-SOI MOSFETs are enhanced compared to the devices fabricated in the control samples and bulk Si. The SiGe layer in strained-SOI can lead to a larger leakage current.