Depth marks on the edge chips for subsequent alignment of opaque layers

A method of manufacturing a semiconductor element (100), wherein: • a substrate (102) is provided which includes a plurality of the regions (105) and at least one edge region (103) with areas of incomplete This or unused substrate areas, each of the region (105) comprises alignment marks range (104) and a device region (106); • a first insulating layer (116) is formed over the substrate; • at least one first alignment mark (114) above the alignment mark region (104) of each die region (105) and a plurality of first conductive lines (112) over the device region (106) of each die region (105) within the first insulating layer (116) is formed, wherein forming the at least one first alignment mark (114) comprises filling the at least one first alignment mark (114) with a conductive material; • at least one second alignment mark (140) within at least the first insulating layer (116) over the at least one edge region (103) of the substrate is formed, wherein the at least one second alignment mark (114) a trench having ...