Influence of the Interface Charges' Location on the Threshold Voltage of TFT

With the development of VLSI (Very Large Scale Integration), the size of devices decreases and the electric field of gate oxide increases relatively. The degradation of TFT (Thin Film Transistor) devices is further affected by NBTI effect. When the device DB-NBTI degenerates, interface charges distribution is non-uniform. In this paper, the gate of p-type silicon TFT device is divided into several grid segments, and different concentration of interface charges is introduced to simulate the non-uniform distribution of charge. The relationship between the interface charges’ location and the threshold voltage is well simulated numerically, in which the conditions of drain biasing, interface charges’ concentration and with or without traps are considered. It is found that the device transfer characteristics lag behind those without considering the trap model. The influence of non-uniform interface charges on the threshold voltage of TFT is stronger near the source and weaker near the drain. When the drain voltage increases, the influence is suppressed to some extent. At the same time, the influence of interface charges on pMOS and TFT are compared and analyzed. The proposed work can promote the research on Drain Bias-Negative Bias Temperature Instability (DB-NBTI) effect.