Design-technology co-optimization of sequential and monolithic CFET as enabler of technology node beyond 2nm

Due to a slowdown in gate pitch scaling linked to fundamental physical limitation, standard cell height reduction is needed to achieve the scaling targets. The complementary FET consisting of stacked NMOS on PMOS device is evaluated for both monolithic and sequential integration. Due to double MOL level access, both CFET options combined with buried power rails reduce the standard cell track height down to 4T, also reducing the routing layer usage within the standard cell. The main advantages of sequential CFET over monolithic is the independent optimization of the top and bottom devices, and the possibility of split gate implementation which offers an area gain in complex cells such as flops, at the expenses of higher cost and process complexity.