Parallel distributed arithmetic FIR filter design based on 4:2 compressors on Xilinx FPGAs

Distributed arithmetic (DA) algorithm is widely used for finite impulse response (FIR) filter implementation. In the beginning, DA was proposed as sequential DA (SDA), and then was extended to parallel DA (PDA) for higher throughput. This paper presents a novel PDA FIR filter architecture based on 4:2 compressors which can be mapped on Xilinx FPGAs efficiently. On average, our proposed FIR architectures achieve 17.5% reduction in resource usage and 20.7% improvement in performance compared to the state-of-the-art PDA FIR filter. Also, on average, there is 57.9% reduction in resource usage and 23.0% improvement in performance compared to PDA FIR filters generated by Xilinx Coregen.