65nm Cu Integration and Interconnect Reliability in Low Stress K=2.75 SiCOH
2006
A low tensile stress SiCOH dielectric with K=2.15 has been developed for implementation in the 2times and 4times fatwire levels for enhanced RC performance in the 65nm technology node. Integration challenges related to mechanical integrity and process-induced damage were successfully overcome. Yield and interconnect reliability metrics comparable to dense K=3 SiCOH have been achieved. Package deep thermal cycle showed sensitivity to assembly which is controllable though chip edge structural engineering
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