Self-aligned tungsten strapped source/drain and gate technology realizing the lowest sheet resistance for sub-quarter micron CMOS

This paper describes a self-aligned tungsten strapped source/drain and gate with the lowest sheet resistance for subquarter micron CMOS. Vapor HF selective etching was applied for grooved gate structure fabrication. Selective tungsten chemical vapor deposition (W-CVD) with high pressure nucleation step was applied to fabricate tungsten strapped CMOS with recessed tungsten on poly-Si gate. The sheet resistances of 0.125 /spl mu/m wide gate and 0.25 /spl mu/m wide diffusion layer were 0.9 /spl Omega/sq. and 1.8 /spl Omega/sq. for NMOS and PMOS, respectively. This is the lowest among reported values. By using this technology, 0.22 /spl mu/m tungsten strapped CMOS was successfully fabricated. >