Source mask optimization methodology (SMO) and application to real full chip optical proximity correction

Due to the continuous shrinking in half pitch and critical dimension (CD) in wafer processing, maintaining a reasonable process window such as depth of focus (DOF) & exposure latitude (EL) becomes very challenging. With the source mask optimization (SMO) methodology, the lithography process window can be improved and a smaller mask error enhancement factor (MEEF) can be achieved. In this paper, the Tachyon SMO work flow and methodology was evaluated. The optimum source was achieved through evaluation of the critical designs with Tachyon SMO software and the simulated performance was then verified on another test case. Criteria such as DOF, EL & MEEF were used to determine the optimum source achieved from the evaluation. Furthermore, the process variation band (PV-Band) and the number of hot spot (design weak points) were compared between the POR and the optimum source. The simulation result shows the DOF, MEEF & worst PV-Band were improved by 13%, 17% & 12%, respectively with the optimum SMO source. In order to verify the improvement from the optimum SMO at the silicon level, a new OPC model was recalibrated with wafer CD from the optimized source. The OPC recipe was also optimized and a reticle was retrofitted with the new OPC. By comparing the process window, hotspots and defects between the original vs. new reticle, the benefit of the optimized source was verified on silicon.