Memory control method for time de-interleaving in a broadcast receiver

The present invention relates to a memory control station for time interleaving applying byte addressing in the memory access time for the reverse interleaving method in a DMB receiver. In particular, the present invention is that the size changes depending on the time r from r + 15 to the memory to store only the sampled data used for the real time reverse interleaving for 16 frames i value (i.e. the value produced by the mod 15) bytes following the steps that are made up of several segments and, by the byte addressed for each segment and storing the plurality of samples of data at a memory address to access the memory, and a time reverse interleaving rule determined by the value of i for generating a memory address, and one of a plurality of sample data stored at the memory address according to many times if in the sample data, the segment be read from that memory address is a read output and the other is made, including the step of masking of the element constituting the memory, a memory address decoding By greatly reducing the complexity of the group, it is able to greatly reduce the area required when you plan to the DMB receiving chip ASIC. DMB, reverse time interleaving, byte addressable