GPS IF Data Record and Replay System Based on FPGA

The non-reproducibility of the real signals makes on-site debugging more complex, and frequent on-site tests cost a lot, bringing a lot of trouble to the complete performance evaluation of the GPS receiver system. This thesis proposes a GPS IF data record and replay system based on FPGA and USB, describes the system design scheme, analyzes an optimizing design technique which guarantees the continuous, high-speed and stable record and replay of GPS data, and realizes a system in which IF data frequency point and data width can be flexibly adjusted. The tests show that the data record and replay format and results satisfy the design demands; the data format is of high flexibility, the high-speed data record and replay is continuous and stable which meets the performance evaluation demands of the receiver. The flexibility of data format and real-time replay not only enhance its practical value but also set the terms for the GPS and INS joint data record and replay system.