A 7.9μA 4-bit 4Msps successive approximation phase-domain ADC for GFSK demodulator

A 4-bit 4Msps successive approximation (SAR) phase-domain analog-to-digital converter (Ph-ADC) for zero intermediate frequency (IF) Bluetooth low energy (BLE) receivers is proposed. With the SAR operation, the Ph-ADC requires only 52 current elements and 1 comparator, in contrast to the conventional design which needs 260 current elements and 8 comparators. Simulation results show that the digital intensive Ph-ADC consumes only 7.9μA current from a 1.8V supply when implemented in a 180nm CMOS process.