8.4 A 0.33V/-40°C process/temperature closed-loop compensation SoC embedding all-digital clock multiplier and DC-DC converter exploiting FDSOI 28nm back-gate biasing

A 32b SoC is designed in 28nm FDSOI to operate in either an energy-efficiency (EE) mode, at 0.45V, or low-leakage (LL) mode, at 0.33V, with process-temperature compensation. At near threshold, it overcomes low transistor current at negative temperatures, the need for an extra digital supply IO, and the clocking power costs faced by the internet-of-things (IoT) and wearable systems. The system includes: 1) an all-digital single-supply open-loop clock multiplier achieving 1.51 pJ/cycle; 2) a 0.33V/0.45V dual-mode switched-network-capacitor DC-DC down converter from a 1.1V logic supply, reaching 75% conversion efficiency in both modes; 3) a closed-loop low-invasiveness timing monitoring system dynamically compensating device centering and temperature changes, enabling constant frequency operation down to −40°C at 20MHz (1MHz) in EE (LL) mode. The system fully exploits forward body bias (FBB) available in 28nm UTBB FDSOI with LVT transistors.