A Highly Reliable 1.4μm Pitch Via-Last TSV Module for Wafer-to-Wafer Hybrid Bonded 3D-SOC Systems

This paper demonstrates the fabrication of a reliable 0.7µm diameter and 5µm deep (0.7x5µm) via-last module, fitting a 1.4µm TSV pitch. Enabling sub-micron TSV diameters requires a thinner photo resist, however still withstanding the top passivation dielectric etch, the deep silicon etch and the bottom dielectric etch. The actual TSV silicon diameter is 0.8µm just below the top dielectric hard mask, but reduces to 0.7µm in the middle and to 0.65µm at the bottom of the via. The bottom dielectric tri-layer, consisting of an STI oxide, a thin SiN and a PMD oxide layer, is etched using a dedicated three step selective etch recipe. A thin ALD TiN embedded barrier is implemented, assuring good TSV reliability. An alternative and scalable protection of the oxide liner at the top of the TSV during bottom liner etch is worked out. It makes use of an APF strippable amorphous carbon film. Despite the sub-micron TSV diameter, a conventional PVD Ta barrier and PVD Cu seed is still maintained. Discontinuities in the PVD Cu seed are repaired by using a 30nm thin alkaline ECD seed layer enhancement (SLE), resulting in a conformal copper seed all over the TSV and ensuring void less ECD copper fill. Electrical results prove the maturity of this 0.7µm diameter, 1.4µm pitch via-last module. The connectivity of the TSV, from wafer front to back side, has been checked by means of kelvin and daisy chain structures, showing 100% yield and low spread on the measured resistance values. High breakdown voltage of the TSVs is obtained. The integrity of the oxide liner all over the TSV sidewall is proven by means of IV-controlled reliability measurements (IVCTRL). The breakdown voltage Vbd has very little dependence on the applied stress voltage ramp rate, resulting in high field accelerating factor γ, confirming the high TSV liner/barrier reliability.