A 0.02mm 2 fully synthesizable period-jitter sensor using stochastic TDC without reference clock and calibration in 10nm CMOS technology

With the increasing clock speed and complexity of SoCs, measuring clock jitter becomes challenging. To effectively manage the tight jitter performance required by an SoC, the clock quality should be directly evaluated at every point where the clock is used in the SoC. In previous work [1-3], on-chip clock measurements were carried out, but these circuits are difficult to integrate into varied systems due to their special requirements of low-noise analog circuitry, a clean reference clock and additional calibration. We propose a fully synthesizable period jitter sensor (PJS), requiring no analog circuit, reference or calibration by improving upon a stochastic time-to-digital converter (TDC) [4]. The inverter delay chain of the stochastic TDC in [4] has a weakness: it may lose delayed signals due to its lengthy delay chain. It is replaced with a short-pulse delay chain, which does not lose delayed signals under any process, voltage and temperature (PVT) conditions. In addition, the proposed PJS is specified in RTL code and is fully synthesizable. It achieves 0.5ps pp resolution for real-time period jitter measurements when its input clock frequency is 1GHz.