Implementation of FinFET Based Static NCL Threshold Gates: An Analysis of Design Choice

Recent trends in CMOS based synchronous designs, such as high operating frequency and technology scaling, result in intricate clock and power management issues. NULL Convention Logic (NCL) is a clockless paradigm, which promises to tackle many issues that dominate synchronous designs. On the other hand, FinFETs have demonstrated potential to provide better power performance and controllability as technology scales down to deep-submicron region, as compared to CMOS. This paper presents multiple FinFET based implementation models of NCL static threshold gates. The performances of different models are analyzed based on propagation delay, energy consumption, and area utilization. A design guideline is also provided for efficient tradeoffs to achieve best average performance, which can be very useful in designing high-speed low-power digital applications in deep-submicron fabrication technology.