Lightweight Hardware Architecture for Eight-Sided Fortress Cipher in FPGA

In the lightweight domain, various ciphers and their different implementations are introduced to deal with the problem of security in resource scare environment. Eight-sided fortress (ESF) is a lightweight Feistel cipher which uses substitution–permutation network based round function with Serpent Substitution-box(S-box). This work presents a study and comparison of the various hardware architectures of ESF to combat issues of security in an extremely constrained resource environment. For the design of hardware, different techniques of S-box implementation are used. Comparison and evaluation of ESF S-box implementation techniques is done on the basis of latency, throughput, area utilization, and power consumption. It is observed that the Random Access Memory (RAM)-based S-box design gave the best results with the requirement of minimum area for its implementation. This makes it the preferred architecture for resource-limited applications.