ESD reliability of thinner gate oxide in deep-submicron low-voltage CMOS technology

Capacitor-couple technique used to early turn on CMOS on-chip ESD protection circuit and to ensure uniform ESD current distribution is proposed. A timing-original design model is also derived to calculate capacitor-couple efficiency for the ESD protection circuit. Using this capacitor-couple technique, ESD reliability of thinner gate oxide in deep-submicron low-voltage CMOS ICs can be effectively improved.